A laboratory bench in New Jersey, on a white ceramic plate a small flat round package two and a half centimetres wide, a gold ring around a square recess holding a tiny square chip, dark and almost black, with a ring of very thin bond wires to gold contact pads, from its left and right sides two fans of about a dozen narrow flat gold ribbons, a few slightly bent, the package open and bare, fine tweezers in a hand in a thin pale glove, a grey stereo microscope above, a green metal rack with black knobs on plain smooth panels soft behind, cool lamp light.
What it was used for
The memory came out of a US Air Force contract. The original paper by Hanchett, Katz and Yung, presented in October 1968 at the Government Microcircuit Applications Conference, names contract AF33(615)-3491; the Computer History Museum describes its object as a very low-power CMOS memory array developed for the US Air Force. RCA's programme leader Gerald B. Herzog describes the setting: the proposal offered emitter-coupled logic arrays for logic and complementary symmetry arrays for memory, for an Air Force computer that was to run navigation programs; after a little more than 3 years, he says, a working navigational computer was delivered. The array actually built and measured held 72 bits as 8 words of 9 bits, with 432 MOS transistors, a write-in time of 40 ns and a read-out time of 30 ns.
What was new
What characterised it was a complete memory on one chip: the array described carries 288 bits as 16 words of 18 bits, together with decoder and read-write drivers, is read nondestructively and needs a single supply voltage; the cell consists of 6 transistors, 4 for the flip-flop and 2 as a complementary transmission gate. The authors draw the comparison themselves: CMOS is somewhat slower than bipolar, but packs more densely and dissipates far less; all-p-channel MOS memories also pack densely, but their standby dissipation is much higher. The name is older than the memory: on 20 February 1963 Wanlass and Sah presented "Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes" at the ISSCC. The barb: the measured quiescent power of the array that was built is less than 20 microwatts, not in the nanowatt range - the nanowatts belong to the single inverter of 1963.
What the sources leave open: The 1968 paper documents operable arrays of 72 bits; the 288-bit array appears in it as a block diagram and a metallization drawing with the wording that it can be fabricated that way. The Computer History Museum, by contrast, writes that RCA demonstrated a 288-bit static RAM in 1968, and holds such a chip. No customers beyond the Air Force contract are documented.