1981 · Reduced Instruction Set Processor · Work 914 of 1,871
A crowded graduate students' office at a university in Berkeley late on an autumn night, a tiny bare square silicon die nine millimetres across resting on the fingertip of a hand in a plaid flannel shirt sleeve, its surface silver-grey with a bluish-violet sheen, divided into lighter rectangular blocks and fine stripes, a row of minute square pads along its edges, below the hand a small open clear plastic box with three more dies on grey foam, a stereo microscope with its lamp lit, paper coffee cups and a desk lamp on a cluttered desk, a terminal with its dark screen turned away, a window onto the scattered lights of the bay.
What it was used for
RISC-I was a teaching and research artefact, not a product. The design was done at the University of California, Berkeley, in a four-quarter sequence of graduate courses in which students proposed architectural ideas, designed components, integrated them into a chip and finally tested the chip themselves. The report names Jim Peek, Korbin Van Dyke, John Foderaro, Dan Fitzpatrick and Zvi Peshkess as the principal VLSI designers. DARPA funded the work; the design data went to MOSIS at the Information Sciences Institute and to Xerox PARC, which had offered to include the chip in its own fabrication runs. Van Dyke built a demonstration board; on 11 June 1982 the first program ran on it: read characters from a terminal, change them by a simple key, write them back.
What was new
The payoff of the narrow instruction set was area: control took 6 % of the chip, against the more than 50 % the authors give for commercial microprocessors of the day - with 31 instructions, 78 registers in 6 overlapping windows and 44,500 transistors. For the register windows Patterson and Séquin name related machines: the BBN C/70, which allocated new register sets without overlapping them, the Texas Instruments 990/9900 family and, as the machine that came closest to overlapped windows, the Bell Labs MAC-8, whose designers in 1975 chose the rich instruction set over the register file. The IEEE milestone speaks of the first VLSI RISC and sets beside it the never-commercialized IBM 801 and Stanford's MIPS, whose chip ran about 1 year later. The fastest chip tested ran at 1.5 MHz, i.e. 2 microseconds per instruction; the designers had expected 400 nanoseconds.
What the sources leave open: The report contradicts itself on chip size: "about 8 by 10 mm" on page 13, "10.2 by 7.75 mm (406 x 305 mil)" on page 16. The comparative figures against the VAX-11/780 and Z8000 are simulated for RISC-I, not measured, assuming a 400 ns cycle; the MC68000 does not appear in those benchmarks. The 44,500 transistor figure is in the 1982 report, not the 1981 ISCA paper. There was no production run.