1981 · Object-Oriented 32-Bit Processor · Work 913 of 1,871
A computer test laboratory in Oregon in autumn, a grey card cage of large processor boards with one board pulled half out, on it two long narrow white ceramic packages six centimetres long with two rows of silver legs, each with a small square plain smooth gold lid in the middle, seated in pale sockets, a third one lying on the bench beside it, a tall stack of pale green-striped fanfold paper lying face down, a hand in a pale blue shirt sleeve pressing the button of a chrome stopwatch, its face turned away from the lens, cold fluorescent light.
What it was used for
The iAPX 432 was a 32-bit microcomputer family from Intel, intended for original equipment manufacturers who would build it into their own products; the Intellec 432/100 was itself called an "Evaluation and Education System". Documented use: in 1983 the Naval Postgraduate School at Monterey ran Ada benchmarks on an Intel 432/670 with up to 4 General Data Processors, compiling on a host VAX-11/780 before downloading. The thesis took two programs from a performance comparison by the University of California, Berkeley, and cites Patterson: against the 68000 and 8086 the 432 reached about half the throughput. Henry Levy writes that by 1983 there were "over 100 Intel 432 systems in the hands of universities and customers" - a small number by microprocessor standards.
What was new
The 432 put operating-system work into hardware: process dispatching, interprocess communication and storage allocation sat in microcode, together with capability-based addressing and 2^40 bytes of virtual address space. There were no general-purpose registers; it computed on a stack. Levy calls it the "first object-based microprocessor" - the first microprocessor of that kind, not the first architecture of that kind: the same source places the IBM System/38 alongside it and points to the Hydra operating system, whose implementation in silicon began the project in 1975. The expensive operation was the one meant to become cheap: a procedure call took 300 microseconds on early prototypes, under 100 after revision.
What the sources leave open: Levy gives "over 160,000 components" for both GDP chips, the NPS thesis "160,000 transistors on two chips"; the differing counts from Eric Smith's archive are not backed by any listed source. The pin count differs too: 54 in Intel's February 1981 data sheet, 64 in Levy. Total units sold is not documented. The ACM pages for both performance studies were blocked.